![]() ![]() Also RF components are relatively cost sensitive compared to higher end products so silicon interposer needs to be cost competitive with other solutions like organic substrates.1. In addition, warpage issues caused by asymmetric structure of the interposer tend to limit the number of signal layers when decreasing the thickness of the interposer. For instance silicon substrate is a quite lossy material and thin thickness of the insulation layers in the TSV or in the inter-layer dielectrics may induce important signal losses. However, for RF applications silicon interposers are not commonly adopted for the moment due to several reasons and in particular because of some technological limitations such as providing thick metallization levels and using low loss materials. Today such silicon interposer technology have been adopted for large digital components like FPGA and GPU. In addition it allows to embed thin-film devices such as MIM capacitors or spiral inductors which improves further the package density as well as the overall performances of the system thanks to closer proximity between the active chips and the passive elements. The use of existing front-end CMOS fabrication lines to fabricate these interposers allows to realize extremely dense routing levels that are not achievable today with other solutions like organic or ceramic substrates. Such silicon interposer has a main function of I/O redistribution in between the different ICs and also for off chip connections to the external world. With the increase of electronic systems complexity and particularly the I/O counts and pitch reduction of the multiple ICs chips to be integrated in a single module, silicon interposers are becoming an interesting option for complex IC System In Packages (SIP). ![]() Experimental results are presented and discussed in order to give some insight on the impact of the different design parameters on the performances of the inductors. The last part of the work is dedicated to the electrical characterization of the inductor devices in the targeted RF frequency range. Physical and DC electrical characterizations are presented to assess the integrity of the individual technology modules like thick copper RDL and TSV. The second part of the paper focuses on the process used to build the test vehicle, especially the realization of thick copper RDL layers on both sides of the interposer silicon wafer and the TSV-last module. ![]() The structures geometry are designed and optimized, using electromagnetic simulator, to target inductance values in the range of 0.5 to 10 nH while addressing a quality factor greater than 20. To facilitate the design work, parameterized cells were built for each type of inductors. This later doesn't require additional metallization to be realized.Ī dedicated test vehicle was designed to study various inductor types including planar spirals, 3D solenoids and 3D torus. The inductors are built using two thick levels of copper RDL, on both sides of a high resistive silicon substrate and connected by through silicon via-last (TSV-last). In this work we present the design and the fabrication of various design of planar and 3D inductor devices fully compatible with the realization of a silicon interposer that is used to host an RF transmitter system operating in the 0.4 to 1 GHz frequency range. To keep the technology at a reasonable cost these last add-on features need to be fabricated with no or minor additional process steps that the ones needed for the fabrication of the interposer itself. This allows the passive components to be very close to the active chips resulting in highly integrated and high performance systems. Among the advantages of this technology are the capability to fabricate fine-pitch redistribution layers and also to embed high quality passive components inside the interposer. Silicon interposers represents an interesting alternatives to organic packages for the fabrication of complex System In Package (SIP) modules especially for RF application. ![]()
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